Silicon Chip Design Consultant

Andrew Porter

Location: Richmond Hill, London

Andrew Porter has over 20 years of analogue and digital integrated circuit design experience in a wide range of EDA tools and design techniques from simulation to layout, physical verification (DRC, LVS) and parasitic extraction. With a Physics degree from The University of Oxford and a former employee of Cadence Design Systems.

Available for short contracts, design-consultancy, EDA flow and methodology optimization, project management, training, lecturing or technical writing, problem solving and IC design.

Consulting Services: Analogue and Digital Design, Physical Verification (Cadence Assura, Diva, DRACULA, DRC, LVS, Mentor Calibre), Power-rail IR drop analysis: (VoltageStorm), Parasitic Extraction (QRC, RCX, QX), Floorplanning (Encounter, Preview), Place and Route (Encounter, nanoroute etc.), Analog Simulation (Spice), DFM, Physical Design (VXL) and Custom Layout (Virtuoso) or technical author.